The present invention relates to a semiconductor device, and particularly to a process for fabricating a gate-to-drain overlapped metal-oxide-semiconductor (MOS) transistor and a structure thereby.
Lightly doped drain (LDD) structures with complete overlap between a low concentration diffusion region and a gate thereof such as an Inverse-T Lightly Doped Drain structure (ITLDD) and a gate overlapped drain (GOLD) structure have been proposed as ways to improve hot carrier reliability and performance of submicron MOS.
The ITLDD and GOLD structures are disclosed in International Electron Device Meeting (IEDM) Tech. Dig., 1989, pp 769-772, IEDM Tech. Dig., 1986, pp 742-745, IEDM Tech. Dig., 1987, pp 38-41, and IEDM Tech. Dig., 1989, pp 617-620.
FIG. 1 is a cross-sectional view of a conventional MOS transistor of ITLDD structure. Diffusion regions 6 of second conductive type are isolated from each other by the channel region which is formed within a first conductive type semiconductor substrate 1, and an insulation layer 7 is formed on the surface of the substrate 1. An inverse T-shaped gate 9 is disposed over the channel region and the diffusion region adjacent to the channel region, and insulation layer spacer regions 11 are formed on the external side walls of the gate 9. In this case, the diffusion regions 6 include low concentration regions 3 and high concentration regions 5, and the gate 9 and the low concentration regions 3 overlap.
By such structure as stated above, the effect of improving a current characteristic and reducing electric field between the insulation layer and the silicon substrate can be obtained. However, the problem is that gate-to-drain overlap capacitance C.sub.gdo increases by gate-to-drain overlap so as to delay transmission time.